Frame capture of a video documenting the navigation performance of the FPGA-based system. Overlays show the stereo image range map and terrain goodness map derived from it.
Previous and current planetary rovers are limited by the available computational power in space qualified radiation hardened processing. When driving autonomously, the limited computation means that the rover must stop for a substantial period of time while the navigation software identifies a hazard free path using acquired imagery. The resulting limitations on driving duty cycle reduce the rover’s average traverse rate, and this in turn leads operators to prefer manual driving modes (when possible) without the full suite of vision-based safety checks.
The Fast Traverse task is working to eliminate these performance penalties and enable fully autonomous rover navigation with a 100 percent driving duty cycle. This is being accomplished by transitioning compute intensive portions of autonomous navigation processing from the main CPU to a Field Programmable Gate Array (FPGA) co-processor. The team has already implemented, tested, and demonstrated binocular stereo ranging and visual odometry localization on a research rover. What currently takes many seconds or even minutes on state-of-the art radiation hard processors can be accomplished in microseconds using our FPGA implementations. At the conclusion of the project, when we have completed FPGA implementations of some remaining critical components of autonomous navigation, future mobility-based missions will be able to drive faster, drive further, and drive more safely.
